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CONTROL BITS D2 TO D0
FUNCTION(2)
MODE 2 MODE 1 MODE 0
Mode 0 : CVBS (automatic gain) 0 0 0
Mode 1 : CVBS (automatic gain) 0 0 1
Mode 2 : CVBS (automatic gain) 0 1 0
Mode 3 : CVBS (automatic gain) 0 1 1
Mode4: Y (automatic gain) + C (gain channel 2 fixed to GAI2 level) 1 0 0
Mode5: Y (automatic gain) + C (gain channel 2 fixed to GAI2 level) 1 0 1
Mode6: Y (automatic gain) + C (gain channel 2 adapted to Y gain) 1 1 0
Mode7: Y (automatic gain) + C (gain channel 2 adapted to Y gain) 1 1 1
Notes
1. Mode select (see Figs 33 to 40).
2. For modes 0 to 3 use BYPS(SA09,D7) = 0 (chrominance trap active), for modes 4 to 7 use BYPS = 1 (chrominance
trap bypassed).
Table 13 Analog control 1 SA 02, D5 to D3 (see Fig.14)
CONTROL BITS D5 TO D3
DECIMAL VALUE UPDATE HYSTERESIS FOR 9-BIT GAIN
GUDL 2 GUDL 1 GUDL 0
0.... off 0 0 0
....7 ±7 LSB 1 1 1
1998 May 15 43
Philips Semiconductors Product specification
Enhanced Video Input Processor (EVIP) SAA7111A
Table 14 Analog control
CONTROL BITS D7 AND D6
ANALOG FUNCTION SELECT FUSE
FUSE 1 FUSE 0
Amplifier plus anti-alias filter bypassed 0 0
01
Amplifier active 1 0
Amplifier plus anti-alias filter active 1 1
AI22 AI22
handbook, halfpage handbook, halfpage
AD2 AD2
AI21 CHROMA AI21 CHROMA
AI12 LUMA AI12 LUMA
AD1 AD1
AI11 AI11
MGC638
MGC637
Fig.33 Mode 0; CVBS (automatic gain). Fig.34 Mode 1; CVBS (automatic gain).
AI22 AI22
handbook, halfpage handbook, halfpage
AD2 AD2
AI21 CHROMA AI21 CHROMA
AI12 LUMA AI12 LUMA
AD1 AD1
AI11 AI11
MGC639 MGC640
Fig.35 Mode 2; CVBS (automatic gain). Fig.36 Mode 3; CVBS (automatic gain).
AI22 AI22
handbook, halfpage handbook, halfpage
AD2 AD2
AI21 CHROMA AI21 CHROMA
AI12 LUMA AI12 LUMA
AD1 AD1
AI11 AI11
MGC641 MGC642
Fig.37 Mode 4 Y (automatic gain) + C
Fig.38 Mode 5 Y (automatic gain) + C
(gain channel 2 fixed to GAI2 level).
(gain channel 2 fixed to GAI2 level).
1998 May 15 44
Philips Semiconductors Product specification
Enhanced Video Input Processor (EVIP) SAA7111A
AI22 AI22
handbook, halfpage handbook, halfpage
AD2 AD2
AI21 CHROMA AI21 CHROMA
AI12 LUMA AI12 LUMA
AD1 AD1
AI11 AI11
MGC643 MGC644
Fig.39 Mode 6 Y (automatic gain) + C Fig.40 Mode 7 Y (automatic gain) + C
(gain channel 2 adapted to Y gain). (gain channel 2 adapted to Y gain).
17.2.3 SUBADDRESS 03
Table 15 Analog control 2 (AICO2) SA03
FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT
Static gain control channel 1 (GAI18) (see SA04)
Sign bit of gain control GAI18 see Table 16 D0
Static gain control channel 2 (GAI28) (see SA05)
Sign bit of gain control GAI28 see Table 17 D1
Gain control fix (GAFIX)
Automatic gain controlled by MODE 1 and MODE 0 GAFIX 0 D2
Gain control is user programmable via GAI1 + GAI2 GAFIX 1 D2
Automatic gain control integration (HOLDG)
AGC active HOLDG 0 D3
AGC integration hold (freeze) HOLDG 1 D3
White peak off (WPOFF)
White peak control active WPOFF 0 D4
White peak off WPOFF 1 D4
Vertical blanking select (VBSL)
Long vertical blanking VBSL 0 D5
Short vertical blanking VBSL 1 D5
HL not reference select (HLNRS)
Normal clamping by HL not HLNRS 0 D6
Reference select by HL not HLNRS 1 D6
1998 May 15 45
Philips Semiconductors Product specification
Enhanced Video Input Processor (EVIP) SAA7111A
17.2.4 SUBADDRESS 04
Table 16 Gain control analog (AIC03); static gain control channel 1 GAI1 SA 04, D7 to D0
SIGN
CONTROL BITS D7 TO D0
DECIMAL GAIN
BIT
VALUE (dB)
GAI18 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10
0.... -5.98 0 0 0000000
....255 0 0 1 1111111
256.... 0 1 0 0000000
....511 5.98 1 1 1111111
17.2.5 SUBADDRESS 05
Table 17 Gain control analog (AIC04); static gain control channel 2 GAI2 SA 05, D7 to D0
SIGN BIT
CONTROL BITS D7 to D0
DECIMAL GAIN
(SA 03, D1)
VALUE (dB)
GAI28 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20
0.... -5.98 0 0 0 0 0 0 0 0 0
....255 0 0 1 1 1 1 1 1 1 1
256.... 0 1 0 0 0 0 0 0 0 0
....511 5.98 1 1 1 1 1 1 1 1 1
17.2.6 SUBADDRESS 06
Table 18 Horizontal sync begin SA 06, D7 to D0
CONTROL BITS D7 to D0
DELAY TIME
(STEP SIZE = 8/LLC)
HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0
-128...-108 forbidden (outside available central counter range)
-107... 1 0 0 1 0101
...108 (50Hz) 0 1 1 0 1100
...107 (60Hz) 0 1 1 0 1011
109...127 (50Hz)
forbidden (outside available central counter range)
108...127 (60Hz)
1998 May 15 46
Philips Semiconductors Product specification
Enhanced Video Input Processor (EVIP) SAA7111A
17.2.7 SUBADDRESS 07
Table 19 Horizontal sync stop SA 07, D7 to D0
CONTROL BITS D7 to D0
DELAY TIME
(STEP SIZE = 8/LLC)
HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0
-128...-108 forbidden (outside available central counter range)
-107... 1 0 0 1 0 1 0 1
...108 (50Hz) 0 1 1 0 1 1 0 0
...107 (60Hz) 0 1 1 0 1 0 1 1
109...127 (50Hz)
forbidden (outside available central counter range)
108...127 (60Hz)
17.2.8 SUBADDRESS 08
Table 20 Sync control SA 08, D7 to D5, D3 to D0
FUNCTION BIT NAME LOGIC LEVEL CONTROL BIT
Vertical noise reduction (VNOI)
Normal mode VNOI1 0 D1
VNOI0 0 D0
Searching mode VNOI1 0 D1
VNOI0 1 D0
Free running mode VNOI1 1 D1
VNOI0 0 D0
Vertical noise reduction bypassed VNOI1 1 D1
VNOI0 1 D0
Horizontal PLL (HPLL)
PLL closed HPLL 0 D2
PLL open, horizontal frequency fixed HPLL 1 D2
TV/VTR mode select (VTRC)
TV mode VTRC 0 D3
(recommended for poor quality TV signals only)
VTR mode (recommended as default setting) VTRC 1 D3
Extended loop filter (EXFIL)
Word width of the loop filter (LF2) amplification = 16-bit EXFIL 0 D5
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